1. Field of the Invention
The present invention relates to the field of circuit partitioning. More specifically, the present invention relates to the partitioning of a circuit design for the purpose of implementing or emulating the circuit design using a number of reconfigurable logic devices.
2. Background Information
FIG. 1 illustrates a typical prior art approach to partitioning a circuit design for the purpose of implementing or emulating the circuit design using a number of reconfigurable logic devices, such as field programmable gate arrays (FPGA). As illustrated, because of the complexity of modern day circuit designs, typically, a circuit design, such as integrated circuit (IC) design 102 having multiple functional blocks (FB), FB-a 104a, FB-b 104b, and so forth, would be provided to a partitioner, such as partitioner 104, along functional block lines, and correspondingly partitioned. For example, a processor design having an instruction fetch and dispatch block, an arithmetic logic unit (ALU), a floating point processing unit (FPU), an on-chip cache memory block, a bus interface unit, and so forth, would be provided to partitioner 104 along these functional block lines, and correspondingly partitioned.
As illustrated, the partitioning would result in x1 partitions 106a for FB-a 104a, x2 partitions 106b for FB-b 104b and so forth. The partitions would be provided in turn to a xe2x80x9ccompilerxe2x80x9d, such as compiler 108, to be correspondingly compiled into a number of corresponding configuration files 110a-110n for configuring the reconfigurable logic resources of a number of corresponding logic devices to correspondingly implement or realize the constituting elements of the corresponding partitions 106a-106n of the function blocks 104a-104n. In other words, for x1, x2, . . . xn partitions 106a-106n for FB-a 104a through FB-n 104n, x1, x2, . . . xn configuration files for a total of x1+x2+ . . . xn logic devices would result.
This prior art partitioning approach may be inefficient in its usage of reconfigurable logic devices for various circuit designs, especially for IC designs where the partitioning of each function block results in one or more xe2x80x9csmallxe2x80x9d partitions of consituting elements. Examples of IC designs where such phenomenon may occur include but are not limited to IC designs having multiple clock domains. In the multiple clock domain case, while the majority of the constituting elements of a functional block would operate in one clock domain, for various purposes, e.g. for interfacing with other function blocks that operate in other clock domains, each function block typically has small groups of consituting elements that operate in one or more of the other clock domains. Since each reconfigurable logic device typically supports only a single clock domain, accordingly the xe2x80x9csmallxe2x80x9d partitions of constituting elements are resulted.
As those skilled in the art would appreciate that corresponding implementation or realization of these xe2x80x9csmallxe2x80x9d partitions of constituting elements in corresponding logic devices often results in leaving a substantial amount of the reconfigurable logic resources of the corresponding logic devices unused. The amount of left over or wastage increases over time, as successive generations of reconfigurable logic devices tend to be equipped with more and more reconfigurable logic resources.
Accordingly, an improved approach to partitioning a circuit design for implementation or emulation on a number of reconfigurable logic devices is desired.
A first and a second netlist of a first and a second function block of a circuit design are correspondingly partitioned into at least a first and a second partition, and a third and a fourth partition respectively. The first and third partitions include majorities of the constituting elements of the first and second netlists respectively. The second and fourth partitions include minorities of the constituting elements of the first and second netlists. Placements of the constituting elements of the first and third partitions are correspondingly determined. The second and fourth partitions are merged to form a composite partition, which in turn is partitioned for joint determination of placement of these minority constituting elements of the first and second netlists of the first and second function blocks on logic devices.
In one embodiment, the second and fourth partitions operate in the same clock domain, while the first and third partitions operate in one or more other clock domains.